1. Field of the Invention
The present invention relates generally to a method of forming a semiconductor package and the structures formed thereby. More particularly, the invention relates to small package outlines and chip scale packages and methods of forming substantially chip scale packages of reduced size and number of parts.
2. State of the Art
In semiconductor manufacture, a single semiconductor die or chip bearing one or more integrated circuits is typically mounted within a sealed package. The package generally protects the die from physical damage and from contaminants, such as moisture or chemicals, found in the surrounding environment. The package also provides a lead system for connecting electrical devices (e.g., the integrated circuits) formed on the active surface of the die to a printed circuit board or other external circuitry. Semiconductor packages containing integrated circuit dice for a broad range of purposes are currently mass produced. Small, but measurable, savings in the packaging of one such semiconductor die or integrated circuit can generate large overall cost savings, due to large production volumes, if the reduced-cost packaging affords required package integrity and thus a high-percentage yield. Further, reduction in package size can eliminate size-based restrictions for use of a die on ever more crowded carrier substrates, such as printed circuit boards (PCBs), where available xe2x80x9creal estatexe2x80x9d is at a premium. Therefore, continual cost and quality improvements in the manufacture of these semiconductor packages, as well as a decrease in the overall dimensions of such packages, are of great value in the semiconductor manufacturing field.
Referring to FIG. 1, an exemplary prior art leadframe 18 used in assembling a conventional semiconductor package is shown. In the center of leadframe 18 is a die paddle 19, located between side rails 20 and 20xe2x80x2 and held by a pair of tie bars 21 and 21xe2x80x2. The die paddle 19 will support a semiconductor chip 30 thereon once the semiconductor package is assembled, as shown in FIG. 2. Leadframe 18 also includes a plurality of leads 23 having inner lead ends 22 extending peripherally about die paddle 19. Extending outward from the inner lead ends 22 of leads 23 is a plurality of outer lead ends 24 that are connected to each other by means of dam bars 26.
FIG. 2 illustrates a sectional view of a semiconductor package 28 produced using the leadframe 18. Prior to the formation of the package 28, the inner lead ends 22 are electrically connected to a plurality of bond pads 32 of the semiconductor die or chip 30 by means of a plurality of metal bond wires 36, typically of gold, aluminum, or alloys thereof. Opposing ends of the metal bond wires 36 are bonded to the bond pads 32 of the semiconductor chip 30 and to the inner lead ends 22, as known in the art. In forming the package 28, the semiconductor chip 30 is fixedly attached, typically with a conductive die-attach epoxy 40, to the top surface of the die paddle 19 of the leadframe 18. The semiconductor chip 30, the inner lead ends 22, and the metal bond wires 36 are then hermetically packaged using a filled-polymer molding compound to form a package body 42. The outer lead ends 24 of the leadframe 18 extend to the outside of the package body 42, usually at opposite sides of the package body 42. Once formation of the semiconductor package 28 is complete, including a trim and form operation to separate the package from the leadframe strip, removal of dam bars 26 and deformation of outer lead ends 24 to desired orientations and shapes, the semiconductor package 28 is mounted and electrically connected to the surface of a PCB (not shown) by securing the outer lead ends 24 to conductive traces on the surface of the PCB.
During the formation of package body 42, a molten particulate-filled polymer is transferred under pressure from a reservoir into a mold (not shown) which surrounds the metal bond wires 36, the semiconductor chip 30, and portions of leadframe 18 (e.g., the inner lead ends 22). The polymer compound used during the transfer mold process is relatively viscous, and the flow front of the material has been known to displace or damage metal bond wires 36 during the mold-fill process. This is commonly referred to as xe2x80x9cbond wire sweepxe2x80x9d or as the xe2x80x9cwire washxe2x80x9d problem. More specifically, when encapsulating a bare die assembly, the die assembly is generally placed in a mold wherein a molten filled-polymer encapsulating material is injected into the mold to surround the die assembly as it conforms to the interior cavity of the mold. However, the encapsulant flow front attendant to this process causes stresses on the bond wires. Since the molten encapsulating material is viscous and due to the orientation of the bond wires, it tends to place forces transverse to at least some of the bond wires as the encasing material is injected into the mold. These directional forces cause the bond wires to flex, which can, in turn, cause the bond wires to break, disconnect from their bond sites, or short with adjacent bond wires or bond pads.
To prevent wire wash damage, some manufacturing processes apply a protective low-viscosity glue or other topping material 46 (thickness exaggerated in FIG. 2) over the metal bond wires 36 before injecting the plastic. This glue and the process of applying it are both called glob-topping. Such preliminary topping before transfer molding freezes the wires in position and effectively protects the metal bond wires 36 during the transfer molding step.
Although the aforementioned semiconductor packages are widely used, they possess a number of shortcomings. For example, as previously described, the typical leadframe 18 used in package 28 has a die paddle 19 for holding the semiconductor chip 30 thereon. Due to differences in the coefficient of thermal expansion between components in the semiconductor package (i.e., the die paddle 19, the semiconductor chip 30, and the die-attach epoxy 40), semiconductor chip 30 may crack and interfacial separation between these components may occur. Also, use of a transfer-molded encapsulant for the package inevitably increases the overall size of the package, which results in waste of space when the package is mounted on the surface of the PCB. The relatively large number of packaging steps and components associated with transfer molding increases both cost and the likelihood of package failure. Further, as chips become more complex, such as higher memory capacity DRAMs, the increased size of a chip may preclude effective transfer-molded packaging within the parameters of a preset exterior package size implemented for earlier generations of lower-capacity memory chips. Another disadvantage seen in fabrication of semiconductor packages according to these traditional principles is the requirement of not only numerous, but specialized, fabrication steps which increase the cost and time of production. Additionally, once a transfer-molded package is formed, the package cannot be disassembled without damaging the enclosed components, making repairs or modifications to components within the finished package impossible.
In view of the foregoing limitations, there is a need in the semiconductor art for an improved method for forming semiconductor packages of compact size (xe2x80x9cchip scale packagesxe2x80x9d) and including a minimal number of component parts. Such needed compact packages may include, by way of example, fine ball grid array packages, or xe2x80x9cFBGAsxe2x80x9d. Specifically, there is a need for an improved method for forming chip scale packages which are adaptable to carrier substrate surfaces having connection points of varying alignment and spacing configurations. There is a further need for an improved method for forming a chip scale package that does not require formation of a protective package body through transfer molding.
The present invention is directed to an improved method for forming a semiconductor chip package having a dimension which lies within a periphery substantially defined by the outside boundaries of the semiconductor chip contained therein. The improved method begins with the application of an adhesive on the active surface of a semiconductor chip to form a patterned adhesive layer on a portion of the active surface and an adhesive-free area wherein the bond pads of the semiconductor chip are located. A leadframe having leads with inner lead ends and outer lead ends is provided. The inner lead ends of the leads are aligned proximate to the adhesive-free area and the leads are attached to the adhesive layer on the active surface of the semiconductor chip. The outer lead ends are formed to have a width which is equal to, and does not extend substantially beyond, the width of the semiconductor chip, thus forming a footprint for the package which is no larger than the dimensions of the semiconductor chip. The bond pads of the semiconductor chip are then interconnected to the inner lead ends of the leads by wire bonding and the bond wires are then encapsulated, as by a silicon mass commonly referred to as a xe2x80x9cglob-topxe2x80x9d. In some embodiments, the packaged semiconductor chip is configured as a ball grid array (BGA) package, including an FBGA.
In another embodiment, the glob-topping step is deleted. Instead, the outer lead ends of the leads are formed to receive and hold a cap. The cap is provided to protect the active surface of the semiconductor chip, thus obviating the need for glob-topping.
In yet another embodiment, after application of the adhesive layer to the active area of the semiconductor chip, tape automated bonding (TAB) tape leads in the form of metal traces carried by a flexible polymer film are then bonded to metal bumps formed on bond pads or, alternately, are bonded to the bond pads through bumps formed on TAB tape leads. TAB tape leads are then attached to the adhesive layer on the semiconductor chip. In yet another embodiment, a cap can be attached to the TAB tape leads by wrapping and adhering an outer portion of the TAB tape around the cap.
In alternate embodiments of the invention, the adhesive is applied on the leads or TAB tape leads, rather than the active surface of the semiconductor chip.
The resulting packaged chip structures created by the aforementioned methods are also contemplated as included within the present invention.